Cache is used as temporary storage for frequently accessed instructions and/or data. When a cache client such a control processing unit (CPU) wishes to access an instruction or data, it first checks the cache. If a cache line in the cache includes a tag matching that of the desired instruction or data, the instruction or data in the cache line is read and used. Otherwise, the instruction or data is fetched from main memory or a higher level cache and inserted in a cache line and used. Subsequent access to the instruction or data is then provided through the cached copy.
In one instance, when an instruction or data address is marked with a breakpoint, address comparisons between each instruction or data address and pre-stored addresses in an address register are repeatedly performed over a set of debug registers to locate the instruction or data address marked with the breakpoint. For an instruction or data address that matches an address in the address register, when the instruction or data address is read, an interrupt is thrown and the processor switches context and begins execution of an interrupt handler. Since the address comparison is performed for all of the instructions and data addresses, this approach may be relatively slow, depending on the number of instructions and data addresses and/or the number of addresses in the address register.